Projects


Lawrence Berkeley National Lab

OpenSoC Fabric

Recent advancements in technology scaling have shown a trend towards greater integration with large-scale chips containing thousands of processors connected to memories and other I/O devices using non-trivial network topologies. Software simulation proves insufficient to study the tradeoffs in such complex systems due to slow execution time, whereas hardware RTL development is too time-consuming. We present OpenSoC Fabric, an on-chip network generation infrastructure which aims to provide a parameterizable and powerful on-chip network generator for evaluating future high performance computing architectures based on SoC technology. OpenSoC Fabric leverages a new hardware DSL, Chisel, which contains powerful abstractions provided by its base language, Scala, and generates both software (C++) and hardware (Verilog) models from a single code base. The OpenSoC Fabric infrastructure is modeled after existing state-of-the-art simulators, offers large and powerful collections of configuration options, and follows object-oriented design and functional programming to make functionality extension as easy as possible.

Publications
  • Coming soon!
Links

BEEcube, Inc.

miniBEE4 FPGA Platform

miniBEE4, much like the BEE4, is a high-performance FPGA-based computing, prototyping, and emulation platform featuring the Xilinx Virtex-6 family of FPGAs made portable. It offers application flexibility and customization as well as significant throughput capacity in a smaller footprint. miniBEE4 is made up of two fundamental components: the COM Express Processing System and FPGA Processing System.

The COM Express Processing System is a COM Express Type 6 unit based on the PICMG® COM.0 Revision 2.0 specification, which provides a computer-on-module (COM) with all components necessary for a bootable host computer, packaged as a super component. The COM Express integrates core CPU and memory functionality, USB, Ethernet, DisplayPort, and PCI-Express. COM Express supports the Intel i7 (i7-2715QE and i7-2655LE) and Intel i5 (i5-2515E) CPUs, as well as up to 4 GB to 8 GB of memory. The 16-lane Gen 2 PCI Express Graphics slot is exposed on miniBEE4 to provide PCI Express expansion (GPU Co-processing, 10Gb Ethernet, etc.). There is also a 4-lane Gen 2 PCI Express connection between the COM Express and the FPGA.

The FPGA Processing System is comprised of one Virtex-6 FPGA. Any currently available Virtex-6 FPGA in the FF1759 flip-chip fine-pitch BGA package is supported, which includes the LX240T, LX365T, LX550T, SX315T, and SX475T devices in all commercial speed grades. Peripheral components attached to the FPGA also include two independent channels of server-class DDR3 SDRAM memory (one ECC RDIMM per channel), four SFP+ connectors for high-speed serial communication, one FMC (VITA 57.1) HPC connector for expansion board support, one 1000Base-T Ethernet PHY, four channels of 10GBase-T Ethernet, and one RTC/EEPROM device. As mentioned before, there is also a 4-lane Gen 2 PCI Express connection between the FPGA and the COM Express.

miniBEE4 can be an "all-in-one" oscilloscope, logic analyzer, spectrum analyzer, signal/pulse generator and arbitrary waveform generator. miniBEE4 was designed for applications as standalone test equipment or networking switch/router equipment as it provides a powerful PC and a reconfigurable FPGA to make prototyping much easier.

Publications
  • UM105: miniBEE4 Hardware Platform User Manual
  • GS102: Getting Started with the miniBEE4 Hardware Platform
Links

BEE4 FPGA Platform

The BEE4 (Berkeley Emulation Engine 4) is a high-performance FPGA-based computing, prototyping, and emulation platform featuring the Xilinx Virtex-6 family of FPGAs. Emphasis is placed at all levels of the design on high throughput data interfaces, processing quadrant homogeneity, reliability, and expandability.

The fundamental component of the BEE4 hardware platform is the main processing board. The main processing board is logically divided into global management circuitry and four identical FPGA processing quadrants. The global management circuitry on the main processing board is responsible for the power distribution, clock distribution, voltage/temperature monitoring, USB host PC interfaces, FPGA programming/debug interfaces, and the distribution of a larger number of control signals between components on the main board.

Each of the four FPGA processing quadrants is identical in terms of features, components, and pinouts. One Virtex-6 FPGA is the center of each processing quadrant. Any currently available Virtex-6 FPGA in the FF1759 flip-chip fine-pitch BGA package is supported, which includes the LX240T, LX365T, LX550T, SX315T, and SX475T devices in all commercial speed grades. Peripheral components attached to each FPGA include independent channels of DDR3 SDRAM memory (one ECC RDIMM per channel), one 8-lane Gen 2 PCI Express connector, two QSFP connectors for high-speed serial communication, one FMC (VITA 57.1) High Pin Count connector for expansion board support, one 1000Base-T Ethernet PHY, and one RTC/EEPROM.

Publications
  • UM103: BEE4 Hardware Platform User Manual
  • GS101: Getting Started with the BEE4 Hardware Platform
Links

Berkeley Wireless Research Center

BEE3 Embedded Controller

The purpose of this project was to develop an x86-based Embedded Controller for the Berkeley Emulation Engine Revision 3 (BEE3) to have a free standing FPGA research platform.

UC Berkeley - Student

EE192 Autonomous Race Car

In the Spring of 2009, I was enrolled in EE192, Mechatronics Design Lab, at the University of California, Berkeley. This class is a design project course focusing on application of theoretical principles in electrical engineering and computer science to control of mechatronic systems incorporating sensors, actuators and intelligence. This course gives you a chance to use your knowledge of (or learn about) power electronics, filtering and signal processing, control, electromechanics, microcontrollers, and real-time embedded software in designing a racing robot.

Publications
Links

EE105 AM Radio Receiver

In the Spring of 2008, I was enrolled in EE105, Microelectronic Devices and Circuits, at the University of California, Berkeley. The class was primarily focused on characterizing circuits; we were asked to analyze, build, and characterize a number of different amplifiers and biasing circuits. For the final project, we were commissioned to design, build, and analyze your own amplifier for an AM receiver, capable of amplifying a small-amplitude signal from an AM transmission (in the 520 kHz to 1610 kHz range) and driving a low-impedance speaker.

Publications
Links

CS150 Wireless Video Conferencing

In the Spring of 2008, I was also enrolled in CS150, Components and Design Techniques for Digital Systems, at the University of California, Berkeley. That semester the project was to create a Wireless Video Conferencing using the Calinx2+ FPGA board.

Publications
Links

Santa Rosa Junior College

Annual Agilent-MESA Lego Robotics Competition - Spring 2007

In Spring 2007, I competed in the Agilent-MESA Lego Robotics Competition at Santa Rosa Junior College. Using the LEGO Mindstorms NXT kits, we built autonomous robots for two competitions: Pit of Despair and Triangle of Confusion.

Publications
  • There are no publications available at this time.
Links

Annual Agilent-MESA Lego Robotics Competition - Spring 2006

In Spring 2006, I competed in the Agilent-MESA Lego Robotics Competition at Santa Rosa Junior College. Using the LEGO Mindstorms RCX kits, we built autonomous robots for two competitions: a Relay Race and Sumo competition.

Publications
Links

High School

Mini Sumo Robot

During Fall 2004 and Spring 2005, I gathered a few of my fellow students and competed in the San Francisco State University, School of Engineering - Robotic Competition. The challenge is to build, from the kit, a 2-wheel robot that can move in all directions. It has a photo cell that can sense different levels of light and react to it. The kit is provided by SFSU to participating teams. The robots participated in an elimination tournament.

Publications

P.O.T.U.S. Chart

During Spring 2005, I compiled a list of all of the Presidents of the United States for my AP US History class containing basic facts about their presidency, as well as their legacy as a President of the United States.

Publications